16Gb: x4, x8 TwinDie DDR4 SDRAM
Description
TwinDie™ 1.2V DDR4 SDRAM
MT40A4G4 – 128 Meg x 4 x 16 Banks x 2 Ranks
MT40A2G8 – 64 Meg x 8 x 16 Banks x 2 Ranks
Description
Options
Marking
• Configuration
– 128 Meg x 4 x 16 banks x 2 ranks
– 64 Meg x 8 x 16 banks x 2 ranks
• FBGA package (Pb-free)
– 78-ball FBGA
(9.5mm x 13mm x 1.2mm) Die Rev :A
– 78-ball FBGA
(8.0mm x 12mm x 1.2mm) Die Rev :B
• Timing – cycle time1
– 0.750ns @ CL = 18 (DDR4-2666)
– 0.833ns @ CL = 16 (DDR4-2400)
– 0.833ns @ CL = 17 (DDR4-2400)
– 0.937ns @ CL = 15 (DDR4-2133)
– 0.937ns @ CL = 16 (DDR4-2133)
• Self refresh
– Standard
• Operating temperature
– Commercial (0°C ≤ T C ≤ 95°C)
• Revision
The 16Gb (TwinDie™) DDR4 SDRAM uses
Micron’s 8Gb DDR4 SDRAM die (essentially two ranks
of the 8Gb DDR4 SDRAM). Refer to Micron’s 8Gb
DDR4 SDRAM data sheet for the specifications not included in this document. Specifications for base part
number MT40A2G4 correlate to TwinDie manufacturing part number MT40A4G4; specifications for base
part number MT40A1G8 correlate to TwinDie manufacturing part number MT40A2G8.
Features
• Uses 8Gb Micron die
• Two ranks (includes dual CS#, ODT, and CKE balls)
• Each rank has 4 groups of 4 internal banks for concurrent operation
• VDD = V DDQ = 1.2V (1.14–1.26V)
• 1.2V V DDQ-terminated I/O
• JEDEC-standard ball-out
• Low-profile package
• TC of 0°C to 95°C
– 0°C to 85°C: 8192 refresh cycles in 64ms
– 85°C to 95°C: 8192 refresh cycles in 32ms
Note:
4G4
2G8
FSE
NRE
-075E
-083E
-083
-093E
-093
None
None
:A
:B
1. CL = CAS (READ) latency.
Table 1: Key Timing Parameters
Data Rate
(MT/s)
Target tRCD-tRP-CL
-075E
2666
18-18-18
13.50
13.50
13.50
-075
2666
19-19-19
14.25
14.25
14.25
-083E
2400
16-16-16
13.32
13.32
13.32
Speed Grade
Note:
1
tRCD
(ns)
tRP
(ns)
CL (ns)
-083
2400
17-17-17
14.16 (13.75)
14.16 (13.75)
14.16 (13.75)
-093E
2133
15-15-15
14.06 (13.50)
14.06 (13.50)
14.06 (13.50)
-093
2133
16-16-16
15.00
15.00
15.00
1. Refer to the Speed Bin Tables for additional details.
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© 2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
16Gb: x4, x8 TwinDie DDR4 SDRAM
Description
Table 2: Addressing
Parameter
Configuration
Bank group address
Bank count per group
Bank address in bank group
Row address
Column address
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4096 Meg x 4
2048 Meg x 8
128 Meg x 4 x 16 banks x 2 ranks
64 Meg x 8 x 16 banks x 2 ranks
BG[1:0]
BG[1:0]
4
4
BA[1:0]
BA[1:0]
128K A[16:0]
64K A[15:0]
1K A[9:0]
1K A[9:0]
2
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Important Notes and Warnings
Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 1: 78-Ball FBGA Ball Assignments (Top View)
1
2
3
4
5
6
7
8
9
A
A
VDD
VSSQ
NF, NF/
TDQS_c
NF, NF/DM_n/
DBI_n/TDQS_t
VDDQ
DQS_c
DQ1
VSSQ
VSSQ
B
B
VPP
VDDQ
ZQ
C
C
VDDQ
DQ0
DQS_t
VDD
VSS
VDDQ
VSSQ
DQ4/NF
DQ2
DQ3
DQ5/NF
VSSQ
D
D
E
E
VSS
VDDQ
DQ6/NF
DQ7/NF
VDDQ
VSS
CK_t
CK_c
VDD
F
F
C2/ODT1 ODT
VDD
G
G
VSS
C0/CKE1
CS_n
CKE
C1/CS1_n RFU/TEN
H
H
VDD
CAS_n/A15 RAS_n/A16
WE_n/A14 ACT_n
VSS
J
J
VREFCA
BG0
A12/BC_n BG1
A10/AP
VDD
K
K
VSS
BA0
A4
A3
BA1
VSS
RESET_n
A6
A0
A1
A5
ALERT_n
L
L
M
M
VDD
A8
A9
A2
A7
VPP
N
N
VSS
Notes:
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A11
A17/NC
PAR
A13
VDD
1. See the FBGA 78-Ball Descriptions table.
2. Dark balls (with ring) designate balls that are specific to controlling the second die of
the TwinDie package when compared to a monolithic package.
3. A comma “,” separates the configuration; a slash “/” defines a selectable function. For
example: Ball A7 = NF, NF/DM_n/DBI_n/TDQS_t where NF applies to the x4 configuration
only. NF/DM_n/DBI_n/TDQS_t applies to the x8 configuration only and is selectable between NF, DM_n, DBI_n, or TDQS_t via MRS.
4
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Ball Assignments and Descriptions
Table 3: FBGA 78-Ball Descriptions
Symbol
Type
Description
A[17:0]
Input
Address inputs: Provide the row address for ACTIVATE commands and the column address for READ/WRITE commands to select one location out of the memory array in the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/
A16, have additional functions; see individual entries in this table). The address
inputs also provide the op-code during the MODE REGISTER SET command. A16 is
used on some 8Gb and 16Gb parts, and A17 is only used on some 16Gb parts.
A10/AP
Input
Auto precharge: A10 is sampled during READ and WRITE commands to determine whether auto precharge should be performed to the accessed bank after a
READ or WRITE operation (HIGH = auto precharge; LOW = no auto precharge).
A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by the bank group and bank addresses.
A12/BC_n
Input
Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW =
burst-chopped). See the Command Truth Table.
ACT_n
Input
Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along
with CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are treated as row address inputs for the ACTIVATE command. When ACT_n is HIGH
(along with CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14
are treated as normal commands that use the RAS_n, CAS_n, and WE_n signals.
See the Command Truth Table.
BA[1:0]
Input
Bank address inputs: Define the bank (within a bank group) to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determines
which mode register is to be accessed during a MODE REGISTER SET command.
BG[1:0]
Input
Bank group address inputs: Define the bank group to which an ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. Also determines which
mode register is to be accessed during a MODE REGISTER SET command. BG[1:0]
are used in the x4 and x8 configurations.
C0/CKE1,
C1/CS1_n,
C2/ODT1
Input
Stack address inputs: These inputs are used only when devices are stacked;
that is, 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are not
used in the x16 configuration). DDR4 will support a traditional dual-die package
(DDP), which uses these three signals for control of the second die (CS1_n, CKE1,
ODT1). DDR4 is not expected to support a traditional quad-die package (QDP).
For all other stack configurations, such as a 4H or 8H, it is assumed to be a singleload (master/slave) type of configuration where C0, C1, and C2 are used as chip
ID selects in conjunction with a single CS_n, CKE, and ODT.
CK_t,
CK_c
Input
Clock: Differential clock inputs. All address, command, and control input signals
are sampled on the crossing of the positive edge of CK_t and the negative edge
of CK_c.
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Ball Assignments and Descriptions
Table 3: FBGA 78-Ball Descriptions (Continued)
Symbol
Type
Description
CKE
Input
Clock enable: CKE HIGH activates, and CKE LOW deactivates, the internal clock
signals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active
power-down (row active in any bank). CKE is asynchronous for self refresh exit.
After VREFCA has become stable during the power-on and initialization sequence,
it must be maintained during all operations (including SELF REFRESH). CKE must
be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t, CK_c, ODT, RESET_n, and CKE are disabled during power-down. Input
buffers (excluding CKE and RESET#) are disabled during self refresh.
CS_n
Input
Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides for external rank selection on systems with multiple ranks. CS_n is considered part of the command code.
DM_nS
Input
Input data mask: DM_n is an input mask signal for write data. Input data is
masked when DM is sampled LOW coincident with that input data during a write
access. DM is sampled on both edges of DQS. DM is not supported on x4 configurations. LDM_n is associated with DQ[7:0]. The DM, DBI, and TDQS functions are
enabled by mode register settings. See the Data Mask (DM) section.
ODT
Input
On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ,
DQS_t, DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for the x4 and x8 configurations (when the TDQS function is enabled via mode register). The ODT pin will
be ignored if the mode registers are programmed to disable RTT.
PAR
Input
Parity for command and address: This function can be enabled or disabled via
the mode register. When enabled, the parity signal covers all command and address inputs, including RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/
BC_n, BA[1:0], BG[1:0], C0/A18, C1/A19, C2/A20. Control pins NOT covered by the
parity signal are CS_n, CKE, and ODT. Unused address pins that are density- and
configuration-specific should be treated internally as 0s by the DRAM parity logic.
RAS_n/A16,
CAS_n/A15,
WE_n/A14
Input
Command inputs: RAS_n/A16 , CAS_n/A15, and WE_n/A14 (along with CS_n and
ACT_n) define the command and/or address being entered. See the ACT_n description in this table.
RESET_n
Input
Active LOW asynchronous reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation.
RESET_n is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of
VDD; that is, 960 mV for DC HIGH and 240 mV for DC LOW.
TEN
Input
Connectivity test mode: TEN is active when HIGH and inactive when LOW. TEN
must be LOW during normal operation. TEN is a CMOS rail-to-rail signal with DC
HIGH and LOW at 80% and 20% of VDD (960mV for DC HIGH and 240mV for DC
LOW).
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Ball Assignments and Descriptions
Table 3: FBGA 78-Ball Descriptions (Continued)
Symbol
Type
Description
DQ
I/O
Data input/output: Bidirectional data bus. DQ represents DQ[3:0], and DQ[7:0]
for the x4, and x8, respectively. If write CRC is enabled via mode register, the
write CRC code is added at the end of data burst. Any one or all of DQ0, DQ1,
DQ2, and DQ3 may be used to monitor the internal VREF level during test via
mode register setting MR[4] A[4] = HIGH, training times change when enabled.
During this mode, RTT value should be set to High-Z. This measurement is for verification purposes and is NOT an external voltage supply pin.
DBI_n
I/O
DBI input/output: Data bus inversion. DBI_n is an input/output signal used for
data bus inversion in the x8 configuration. DBI_n is associated with DQ[7:0]. The
DBI feature is not supported on x4 configurations. DBI can be configured for
both READ (output) and WRITE (input) operations depending on the mode register settings. The DM, DBI, and TDQS functions are enabled by mode register settings. See the Data Bus Inversion (DBI) section.
DQS_t,
DQS_c
I/O
Data strobe: Output with READ data, input with WRITE data. Edge-aligned with
READ data, centered-aligned with WRITE data. For the x4 and x8 configurations,
DQS corresponds to the data on DQ[3:0] and DQ[7:0] respectively. DDR4 SDRAM
supports a differential data strobe only and does not support a single-ended data
strobe.
ALERT_n
Output
Alert output: This signal allows the DRAM to indicate to the system's memory
controller that a specific alert or event has occurred. Alerts will include the command/address parity error and the CRC data error when either of these functions
is enabled in the mode register.
TDQS_t,
TDQS_c
Output
Termination data strobe: TDQS_t and TDQS_c are used by x8 DRAMs only.
When enabled via the mode register, the DRAM will enable the same RTT termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c.
When the TDQS function is disabled via the mode register, the DM/TDQS_t pin
will provide the data mask (DM) function, and the TDQS_c pin is not used. The
TDQS function must be disabled in the mode register for the x4 configuration.
The DM function is supported only in x8 configuration.
VDD
Supply
Power supply: 1.2V ±0.060V.
VDDQ
Supply
DQ power supply: 1.2V ±0.060V.
VPP
Supply
DRAM activating power supply: 2.5V -0.125V / +0.250V.
VREFCA
Supply
Reference voltage for control, command, and address pins.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground.
ZQ
Reference
RFU
–
Reserved for future use.
NC
–
No connect: No internal electrical connection is present.
NF
–
No function: May have internal connection present, but has no function.
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Reference ball for ZQ calibration: This ball is tied to an external 240Ω resistor
(RZQ), which is tied to VSSQ. Note that this ball is shared by two DRAM devices. As
a result, ZQ calibration operations need to be carried out separately so that correct values are achieved.
7
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Functional Description
Functional Description
The TwinDie DDR4 SDRAM is a high-speed, CMOS dynamic random access memory
device internally configured as two 16-bank DDR4 SDRAM devices.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like-die tested within a monolithic die package.
The DDR4 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O balls.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR4 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR4 SDRAM and edge-aligned to the
data strobes.
Read and write accesses to the DDR4 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed
sequence. Operation begins with the registration of an ACTIVATE command, which is
then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVATE command are used to select the bank and row to be accessed. The
address bits (including CSn#, BAn, and An) registered coincident with the READ or
WRITE command are used to select the rank, bank, and starting column location for the
burst access.
This data sheet provides a general description, package dimensions, and the package
ballout. Refer to the Micron monolithic DDR4 data sheet for complete information regarding individual die initialization, register definition, command descriptions, and die
operation.
Industrial Temperature
The industrial temperature (IT) option, if offered, requires that the case temperature
not exceed –40°C or 95°C. JEDEC specifications require the refresh rate to double when
TC exceeds 85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance, IDD values, some IDD specifications and the input/output impedance must be derated when T C is < 0°C or > 95°C. See the DDR4 monolithic data
sheet for details.
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Functional Block Diagrams
Functional Block Diagrams
Figure 2: Functional Block Diagram (128 Meg x 4 x 16 Banks x 2 Ranks)
Rank 1
(128 Meg x 4 x 16 banks)
Rank 0
(128 Meg x 4 x 16 banks)
CKE1
PAR
TEN
ODT1
RESET
CS1#
CS0#
CK
CK#
ZQ
ALERT_n
CKE0
A[13:0],
ACT_n,
WE_n/A14,
CAS_n/A15,
RAS_n/A16,
BA[1:0],
BG[1:0]
ODT0
DM
DQ[3:0]
DQS, DQS#
Figure 3: Functional Block Diagram (64 Meg x 8 x 16 Banks x 2 Ranks)
Rank 1
(64 Meg x 8 x 16 banks)
Rank 0
(64 Meg x 8 x 16 banks)
CS1#
CKE1
ODT1
PAR
TEN
RESET
ALERT_n
CK
CK#
ZQ
CS0#
A[13:0],
ACT_n,
WE_n/A14,
CAS_n/A15,
RAS_n/A16,
BA[1:0],
BG[1:0]
CKE0
ODT0
TDQS#
DQ[7:0]
DBI/DM/TDQS
DQS, DQS#
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – Leakages
Electrical Specifications – Leakages
Table 4: Input and Output Leakages
Symbol
Parameter
Min
Max
Units
Notes
IIN
Input leakage current
Any input 0V ≤ VIN ≤ VDD,
VREF pin 0V ≤ VIN ≤ 1.1V
(All other pins not under test = 0V)
–4
4
µA
1
IVREFCA
VREF supply leakage current
(All other pins not under test = 0V)
–4
4
µA
2
IZQ
Input leakage on ZQ pin
–100
20
µA
ITEN
Input leakage on TEN pin
–12
20
µA
IOZpd
Output leakage: VOUT = VDDQ
–
20
µA
3
IOZpu
Output leakage: VOUT = VSSQ
–100
–
µA
3, 4
Notes:
1.
2.
3.
4.
Any input 0V < VIN < 1.1V
VREFCA = VDD/2, VDD at valid level.
DQ are disabled.
ODT is disabled with the ODT input HIGH.
Temperature and Thermal Impedance
It is imperative that the DDR4 SDRAM device’s temperature specifications, shown in
the following table, be maintained in order to ensure the junction temperature is in the
proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’s thermal impedances correctly. The thermal impedances listed in Table 6 (page 11) apply to the current die revision and packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications,” prior to using the values listed in the
thermal impedance table. For designs that are expected to last several years and require
the flexibility to use several DRAM die shrinks, consider using final target theta values
(rather than existing values) to account for increased thermal impedances from the die
size reduction.
The DDR4 SDRAM device’s safe junction temperature range can be maintained when
the T C specification is not exceeded. In applications where the device’s ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the
case temperature specifications.
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – Leakages
Table 5: Thermal Characteristics
Notes 1–3 apply to entire table
Parameter
Symbol
Value
Units
TC
0 to 85
°C
0 to 95
°C
Operating temperature
Notes:
Notes
4
1. MAX operating case temperature TC is measured in the center of the package, as shown
below.
2. A thermal solution must be designed to ensure that the device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the device exceeds maximum TC during
operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9µs
interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh
(ASR), if available, must be enabled.
Figure 4: Temperature Test Point Location
Test point
Length (L)
0.5 (L)
0.5 (W)
Width (W)
Table 6: Thermal Impedance
Package
78-ball
78-ball
Θ JA (°C/W)
Airflow =
0m/s
Θ JA (°C/W)
Airflow =
1m/s
Θ JA (°C/W)
Airflow =
2m/s
Θ JB (°C/W)
Θ JC (°C/W)
Notes
Low
conductivity
47.9
36.2
32.0
NA
1.6
1
High
conductivity
28.3
23.0
21.3
10.6
NA
Low
conductivity
53.5
41.5
37.0
NA
1.5
High
conductivity
33.2
27.4
25.6
20.2
NA
Substrate
Rev A "FSE"
Rev B "NRE"
Note:
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
1
1. Thermal resistance data is based on a number of samples from multiple lots and should
be viewed as a typical number.
11
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – Leakages
Figure 5: Thermal Impedance
Thermal Impedance (°C/W)
60
53.5
Low conductivity test board
50
High conductivity test board
41.5
37.0
40
33.2
27.4
30
25.6
20.2
20
10
1.5
0
θJA (0 m/s)
Note:
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
θJA (1 m/s)
θJA (2 m/s)
θJB
θJC
1. All simulations are conducted per JEDEC standards.
12
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Characteristics – AC and DC Output Measurement
Levels
Electrical Characteristics – AC and DC Output Measurement Levels
Single-Ended Outputs
Table 7: Single-Ended Output Levels
Parameter
Symbol
DDR4-1600 to DDR4-3200
Unit
DC output high measurement level (for IV curve linearity)
VOH(DC)
1.1 × VDDQ
V
DC output mid measurement level (for IV curve linearity)
VOM(DC)
0.8 × VDDQ
V
DC output low measurement level (for IV curve linearity)
VOL(DC)
0.5 × VDDQ
V
AC output high measurement level (for output slew rate)
VOH(AC)
(0.7 + 0.15) × VDDQ
V
AC output low measurement level (for output slew rate)
VOL(AC)
(0.7 - 0.15) × VDDQ
V
1. The swing of ±0.15 × VDDQ is based on approximately 50% of the static single-ended
output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load
of 50Ω to VTT = VDDQ.
Note:
Using the same reference load used for timing measurements, output slew rate for falling and rising edges is defined and measured between V OL(AC) and V OH(AC) for singleended signals.
Table 8: Single-Ended Output Slew Rate Definition
Measured
Description
From
To
Defined by
Single-ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC) - VOL(AC)]/ΔTRse
Single-ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC) - VOL(AC)]/ΔTFse
Figure 6: Single-ended Output Slew Rate Definition
TRse
Single-Ended Output Voltage (DQ)
VOH(AC)
VOL(AC)
TFse
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
13
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© 2015 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Characteristics – AC and DC Output Measurement
Levels
Table 9: Single-Ended Output Slew Rate
For RON = RZQ/7
DDR4-1333 / 1866 / 2133 / 2400 /2666
Parameter
Single-ended output slew rate
Symbol
Min
Max
Unit
SRQse
2
7
V/ns
1. SR = slew rate; Q = query output; se = single-ended signals
2. In two cases a maximum slew rate of 12V/ns applies for a single DQ signal within a byte
lane:
Notes:
• Case 1 is defined for a single DQ signal within a byte lane that is switching into a certain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ signals in the same byte lane are static (they stay at either HIGH or LOW).
• Case 2 is defined for a single DQ signal within a byte lane that is switching into a certain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ signals in the same byte lane are switching into the opposite direction (from LOW-toHIGH or HIGH-to-LOW, respectively). For the remaining DQ signal switching into the
opposite direction, the standard maximum limit of 7 V/ns applies.
Differential Outputs
Table 10: Differential Output Levels
Parameter
Symbol
DDR4-1600 to DDR4-3200
Unit
AC differential output high measurement level (for output slew
rate)
VOH,diff(AC)
0.3 × VDDQ
V
AC differential output low measurement level (for output slew
rate)
VOL,diff(AC)
–0.3 × VDDQ
V
Note:
1. The swing of ±0.3 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of
50Ω to VTT = VDDQ at each differential output.
Using the same reference load used for timing measurements, output slew rate for falling and rising edges is defined and measured between V OL,diff(AC) and V OH,diff(AC) for differential signals.
Table 11: Differential Output Slew Rate Definition
Measured
Description
From
To
Defined by
Differential output slew rate for rising edge
VOL,diff(AC)
VOH,diff(AC)
[VOH,diff(AC) - VOL,diff(AC)]/ΔTRdiff
Differential output slew rate for falling edge
VOH,diff(AC)
VOL,diff(AC)
[VOH,diff(AC) - VOL,diff(AC)]/ΔTFdiff
PDF: CCMTD-1725822587-6665
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Characteristics – AC and DC Output Measurement
Levels
Figure 7: Differential Output Slew Rate Definition
Differential Input Voltage (DQS_t, DQS_c)
TRdiff
VOH,diff(AC)
VOL,diff(AC)
TFdiff
Table 12: Differential Output Slew Rate
For RON = RZQ/7
DDR4-1333 / 1866 / 2133 / 2400 / 2666
Parameter
Differential output slew rate
Note:
Symbol
Min
Max
Unit
SRQdiff
4
14
V/ns
1. SR = slew rate; Q = query output; diff = differential signals.
Reference Load for AC Timing and Output Slew Rate
The effective reference load of 50Ω to V TT = V DDQ and driver impedance of RZQ/7 for
each output was used in defining the relevant AC timing parameters of the device as
well as output slew rate measurements.
RON nominal of DQ, DQS_t and DQS_c drivers uses 34 ohms to specify the relevant AC
timing paraeter values of the device. The maximum DC high level of output signal = 1.0
× V DDQ, the minimum DC low level of output signal = { 34 /( 34 + 50 ) } × V DDQ = 0.4 ×
VDDQ
The nominal reference level of an output signal can be approximated by the following:
The center of maximum DC high and minimum DC low = { ( 1 + 0.4 ) / 2 } × V DDQ = 0.7 ×
VDDQ. The actual reference level of output signal might vary with driver R ON and reference load tolerances. Thus, the actual reference level or midpoint of an output signal is
at the widest part of the output signal’s eye.
PDF: CCMTD-1725822587-6665
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Characteristics – AC and DC Output Measurement
Levels
Figure 8: Reference Load For AC Timing and Output Slew Rate
VDDQ
CK_t, CK_c
VTT = VDDQ
DQ, DQS_t, DQS_c,
DM, TDQS_t, TDQS_c
DUT
RTT = 50Ω
VSSQ
Timing reference point
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
16
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters
Electrical Specifications – ICDD Parameters
Table 13: DDR4 ICDD Specifications and Conditions (Rev. A)
Note 1 applies to the entire table
Combined
Individual
Symbol
Die Status
Bus
Width
DDR4-2133
DDR4-2400
DDR4-2666
Units
ICDD0
ICDD0 =
IDD0 + IDD2P + 3
x4, x8
83
93
TBD
mA
ICPP0
ICPP0 =
IPP0 + IPP3N
x4, x8
6
6
TBD
mA
ICDD1
ICDD1 =
IDD1 + IDD2P + 3
x4, x8
98
108
TBD
mA
ICDD2N
ICDD2N =
IDD2N + IDD2P
x4, x8
70
80
TBD
mA
ICDD2NT
ICDD2NT =
IDD2NT + IDD2P
x4, x8
80
90
TBD
mA
ICDD2P
ICDD2P =
IDD2P + IDD2P
x4, x8
50
60
TBD
mA
ICDD2Q
ICDD2Q =
IDD2Q + IDD2P
x4, x8
70
75
TBD
mA
ICDD3N
ICDD3N =
IDD3N + IDD2P
x4, x8
80
85
TBD
mA
ICPP3N
ICPP3N =
IPP3N + IPP3N
x4, x8
6
6
TBD
mA
ICDD3P
ICDD3P = IDD3P + IDD2P
x4, x8
60
70
TBD
mA
ICDD4R
ICDD4R =
IDD4R + IDD2P + 3
x4
163
178
TBD
mA
x8
178
183
TBD
ICDD4W =
IDD4W + IDD2P + 3
x4
163
178
TBD
x8
178
193
TBD
ICDD5R
ICDD5R =
IDD5R + IDD2P
x4, x8
89
94
TBD
mA
ICPP5R
ICPP5R =
IPP5R + IPP3N
x4, x8
8
8
TBD
mA
ICDD6N
ICDD6N =
IDD6N + IDD6N
x4, x8
60
60
TBD
mA
ICDD6E
ICDD6E =
IDD6E + IDD6E
x4, x8
70
70
TBD
mA
ICDD6R2
ICDD6R =
IDD6R + IDD6R
x4, x8
50
50
TBD
mA
ICDD6A (25°C)2
ICDD6A =
IDD6A + IDD6A
x4, x8
40
40
TBD
mA
ICDD6A (45°C)2
ICDD6A =
IDD6A + IDD6A
x4, x8
50
50
TBD
mA
ICDD6A (75°C)2
ICDD6A =
IDD6A + IDD6A
x4, x8
70
70
TBD
mA
ICDD4W
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
17
mA
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters
Table 13: DDR4 ICDD Specifications and Conditions (Rev. A) (Continued)
Note 1 applies to the entire table
Combined
Individual
Symbol
Die Status
Bus
Width
DDR4-2133
DDR4-2400
DDR4-2666
Units
ICDD7 =
IDD7 + IDD2P + 3
x4
213
223
TBD
mA
x8
228
238
TBD
ICPP7
ICPP7 =
IPP7 + IPP3N
x4, x8
18
18
TBD
mA
ICDD8
ICDD8 = IDD8 + IDD8
x4, x8
40
40
TBD
mA
ICDD7
Notes:
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
1. ICDD values reflect the combined current of both individual die. IDDx represents individual die values.
2. ICDD6R and ICDD6A values are typical.
18
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© 2015 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters
Table 14: DDR4 ICDD Specifications and Conditions (Rev. B)
Note 1 applies to the entire table
Combined
Individual
Symbol
Die Status
Bus
Width
DDR4-2133
DDR4-2400
DDR4-2666
Units
ICDD0 =
IDD0 + IDD2P + 3
x4
68
71
TBD
mA
x8
73
76
TBD
ICPP0
ICPP0 =
IPP0 + IPP3N
x4, x8
6
6
TBD
mA
ICDD1
ICDD1 =
IDD1 + IDD2P + 3
x4
80
83
TBD
mA
x8
85
88
TBD
ICDD2N
ICDD2N =
IDD2N + IDD2P
x4, x8
58
59
TBD
mA
ICDD2NT
ICDD2NT =
IDD2NT + IDD2P
x4, x8
70
75
TBD
mA
ICDD2P
ICDD2P =
IDD2P + IDD2P
x4, x8
50
50
TBD
mA
ICDD2Q
ICDD2Q =
IDD2Q + IDD2P
x4, x8
55
55
TBD
mA
ICDD3N
ICDD3N =
IDD3N + IDD2P
x4, x8
65
68
TBD
mA
ICPP3N
ICPP3N =
IPP3N + IPP3N
x4, x8
6
6
TBD
mA
ICDD3P
ICDD3P = IDD3P + IDD2P
x4, x8
55
57
TBD
mA
x8
60
62
TBD
ICDD4R
ICDD4R =
IDD4R + IDD2P + 3
x4
138
138
TBD
x8
153
163
TBD
ICDD4W
ICDD4W =
IDD4W + IDD2P + 3
x4
133
141
TBD
x8
143
151
TBD
ICDD5R
ICDD5R =
IDD5R + IDD2P
x4, x8
75
78
TBD
mA
ICPP5R
ICPP5R =
IPP5R + IPP3N
x4, x8
8
8
TBD
mA
ICDD6N
ICDD6N =
IDD6N + IDD6N
x4, x8
60
60
TBD
mA
ICDD6E
ICDD6E =
IDD6E + IDD6E
x4, x8
70
70
TBD
mA
ICDD6R2
ICDD6R =
IDD6R + IDD6R
x4, x8
40
40
TBD
mA
ICDD6A (25°C)2
ICDD6A =
IDD6A + IDD6A
x4, x8
16
16
TBD
mA
ICDD6A (45°C)2
ICDD6A =
IDD6A + IDD6A
x4, x8
40
40
TBD
mA
ICDD0
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
19
mA
mA
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters
Table 14: DDR4 ICDD Specifications and Conditions (Rev. B) (Continued)
Note 1 applies to the entire table
Combined
Individual
Symbol
Die Status
Bus
Width
DDR4-2133
DDR4-2400
DDR4-2666
Units
ICDD6A =
IDD6A + IDD6A
x4, x8
60
60
TBD
mA
ICDD7
ICDD7 =
IDD7 + IDD2P + 3
x4
188
193
TBD
mA
x8
198
203
TBD
ICPP7
ICPP7 =
IPP7 + IPP3N
x4, x8
18
18
TBD
mA
ICDD8
ICDD8 = IDD8 + IDD8
x4, x8
50
50
TBD
mA
ICDD6A
(75°C)2
Notes:
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
1. ICDD values reflect the combined current of both individual die. IDDx represents individual die values.
2. ICDD6R and ICDD6A values are typical.
20
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Package Dimensions
Package Dimensions
Figure 9: 78-Ball FBGA Die Rev. A (package code FSE)
Seating plane
A
78X Ø0.45
Dimensions apply
to solder balls postreflow on Ø0.33 NSMD
ball pads.
0.1 A
Ball A1 ID
(covered by SR)
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
13 ±0.1
9.6 CTR
0.8 TYP
1.1 ±0.1
0.8 TYP
6.4 CTR
0.3 ±0.05
9.5 ±0.1
Notes:
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
21
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Package Dimensions
Figure 10: 78-Ball FBGA Die Rev. B (package code NRE)
Seating plane
A
78X Ø0.47
Dimensions apply
to solder balls postreflow on Ø0.42 SMD
ball pads.
0.12 A
Ball A1 ID
(covered by SR)
9 8
7
3
2
Ball A1 ID
1
A
B
C
D
E
12 ±0.1
F
9.6 CTR
G
H
J
K
L
M
0.8 TYP
N
1.1 ±0.1
0.8 TYP
0.34 ±0.05
6.4 CTR
8 ±0.1
Notes:
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000
www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc. TwinDie is a trademark of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: CCMTD-1725822587-6665
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